Integrated circuits such as programmable integrated circuits may contain volatile memory elements in the form of static random access memory (SRAM) cells. In programmable integrated circuits, SRAM cells may serve as configuration random access memory (CRAM) cells. Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. CRAM cells are used to store configuration data supplied by the user. Once loaded, CRAM cells supply control signals to transistors to configure the transistors to implement the desired logic function.
Volatile memory elements such as SRAM and CRAM cells are typically formed using a pair of cross-coupled inverters. In each memory cell, the pair of cross-coupled inverters is connected to a pair of address transistors that are turned on when data is being read from or written into the memory cell. When no data is being read from or written into the memory cell, the address transistors are turned off to isolate the memory cell.
There is a trend with each successive generation of integrated circuit technology to scale transistors towards smaller sizes, lower threshold voltages, and lower power supply voltages. Lower power supply voltages and smaller devices may lead to decreased read/write margins for volatile memory elements. This can pose challenges for reliable device operation. Moreover, smaller devices tend to suffer more from process, voltage, and temperature variations (PVT variations). Operating the memory elements at lower power supply voltages can further exacerbate the amount of variation experienced by the memory elements, resulting in reduced memory yield.
In an effort to increase memory yield, techniques that adjust memory cell power supply levels have been developed for single-port memory cells. For example, the memory cell power supply voltage is temporarily raised during read operations to enhance read stability, whereas the memory cell power supply voltage is temporarily lowered during write operations to enhance write-ability. This technique, however, cannot be applied to dual-port memory cells (i.e., memory cells having first and second ports each of which can be used to perform a read/write operation independent of the other port), because dual-port memory cells are required to be able to simultaneously read and write data using the two ports. As an example, elevating the power supply level will only facilitate a read access associated with the first port while adversely affecting a write access associated with the second port.